Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures. These architectures are named for the resemblance that the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuits, respectively.
In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (wordlines) and their drains are connected to column bitlines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the wordline connected to their gates. The row of selected memory cells then place their stored data values on the column bitlines by flowing a differing current if in a programmed state or not programmed state from the connected source line to the connected column bitlines.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are connected by rows to wordlines. Each memory cell, however, is not directly connected to a source line and a column bit line. The memory cells of the array are instead arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are connected together in series, source to drain, between a common sourceline and a column bitline. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line connected to their gates. In addition, the wordlines connected to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors and allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the sourceline to the column bitline through each floating gate memory cell of the series connected string, restricted only by the memory cells of each string that are selected to be read. This places the current encoded stored data values of the row of selected memory cells on the column bitlines.
FIG. 1 illustrates a column of a typical prior art NAND flash memory device. The selected wordline for the flash memory cells being programmed is typically biased at a voltage that is greater than 16V. The illustrated wordline 100 of the cell to be programmed is biased at 19V. The unselected wordlines for the remaining cells are typically biased at approximately 10V. As NAND flash memory is scaled, parasitic capacitance coupling 101-104 between the selected wordline and adjacent floating gates (FG) and control gates (CG) becomes problematic. Because of the parasitic coupling, the adjacent cells are more prone to Vpass disturb than the other cells that also share the common bitline with the cells being programmed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to minimize programming induced Vpass and adjacent wordline stress between a selected wordline and adjacent unselected wordlines.